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EN29F040A
EN29F040A 4 Megabit (512K x 8-bit) Flash Memory
FEATURES
* 5.0V operation for read/write/erase operations * Fast Read Access Time - 45ns, 55ns, 70ns, and 90ns * Sector Architecture: 8 uniform sectors of 64Kbytes each Supports full chip erase Individual sector erase supported Sector protection: Hardware locking of sectors to prevent program or erase operations within individual sectors High performance program/erase speed Byte program time: 10s typical Sector erase time: 500ms typical Chip erase time: 3.5s typical * JEDEC Standard program and erase commands * JEDEC standard DATA polling and toggle bits feature * Single Sector and Chip Erase * Sector Unprotect Mode * Embedded Erase and Program Algorithms * Erase Suspend / Resume modes: Read and program another Sector during Erase Suspend Mode * 0.23 m triple-metal double-poly triple-well CMOS Flash Technology * Low Vcc write inhibit < 3.2V * 100K endurance cycle * Package Options - 32-pin PDIP - 32-pin PLCC - 32-pin TSOP (Type 1) * Commercial and Industrial Temperature Ranges
* -
* Low Standby Current - 1A CMOS standby current-typical - 1mA TTL standby current * Low Power Active Current - 30mA active read current - 30mA program/erase current
GENERAL DESCRIPTION
The EN29F040A is a 4-Megabit, electrically erasable, read/write non-volatile flash memory. Organized into 512K words with 8 bits per word, the 4M of memory is arranged in eight uniform sectors of 64Kbytes each. Any byte can be programmed typically in 10s. The EN29F040A features 5.0V voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems. The EN29F040A has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E ) controls, which eliminate bus contention issues. This device is designed to allow either single (or multiple) Sector or full chip erase operation, where each Sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.
This Data Sheet may be revised by subsequent versions 1 or modifications due to changes in technical specifications.
(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
TABLE 1. PIN DESCRIPTION
Pin Name A0-A18 DQ0-DQ7 Function Addresses
A0 - A18 18 8 DQ0 - DQ7 EN29F040A
FIGURE 1. LOGIC DIAGRAM
Vcc
Data Inputs/Outputs Chip Enable Output Enable Write Enable Supply Voltage (5V 10% ) Ground
Vss CE OE WE
CE OE
WE
Vcc Vss
TABLE 2. SECTOR ARCHITECTURE
Sector
7 6 5 4 3 2 1 0
ADDRESSES
70000h - 7FFFFh 60000h - 6FFFFh 50000h - 5FFFFh 40000h - 4FFFFh 30000h - 3FFFFh 20000h - 2FFFFh 10000h - 1FFFFh 00000h - 0FFFFh
SIZE (Kbytes) 64 64 64 64 64 64 64 64
A18 1 1 1 1 0 0 0 0
A17 1 1 0 0 1 1 0 0
A16 1 0 1 0 1 0 1 0
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2004/04/01
EN29F040A
BLOCK DIAGRAM
Vcc Vss
Block Protect Switches
DQ0-DQ7
Erase Voltage Generator State Control Program Voltage Generator Chip Enable Output Enable Logic
STB
Input/Output Buffers
WE
Command Register CE OE
Data Latch
Y-Decoder Address Latch
STB
Y-Gating
Vcc Detector
Timer
X-Decoder
Cell Matrix
A0-A18
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2004/04/01
EN29F040A
FIGURE 2. PDIP
FIGURE 3. PLCC
FIGURE 4. TSOP
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2004/04/01
EN29F040A
TABLE 3. OPERATING MODES 4M FLASH USER MODE TABLE
USER MODE STANDBY READ OUTPUT DISABLE READ MANUFACTURE ID READ DEVICE ID VERIFY SECTOR PROTECTION SECTOR PROTECTION VERIFY SECTOR UNPROTECTION SECTOR UNPROTECTION WRITE
CE
H L L L L L L L Pulse L L
WE
X H H H H H Pulse L H VID L
OE
X L H L L L VID L VID H
A9
X A9 X VID VID VID VID VID L A9
A8
X A8 X L/H L/H X X X X A8
A6
X A6 X L L L L H X A6
A5
X A5 X X X X X X H A5
A1
X A1 X L L H X H X A1
A0
X A0 X L H L X L X A0
Ax/y
X Ax/y X X X X X X X Ax/y
DQ(0-7)
HI-Z DQ (0-7) HI-Z MANUFACTURE ID DEVICE ID (T/B) CODE X CODE X DIN (0-7)
NOTES: 1) L = VIL, H = VIH, VID = 11.0V 0.5V 2) X = Don't care, either VIH or VIL 3) Ax/y: Ax = Addr(x), Ay = Addr(y)
TABLE 4. DEVICE IDENTIFICTION 4M FLASH MANUFACTURER/DEVICE ID TABLE
A8 READ MANUFACTURER ID READ DEVICE ID H H
(1)
A6 L L
A1 L L
A0 L H
(2)
DQ(7-0) HEX MANUFACTURER ID 1C DEVICE ID 04
NOTES: 1) If a Manufacturing ID is read with A8 = L, the chip will output a configuration code 7Fh. A further Manufacturing ID must be read with A8 = H. 2) If a Device ID is read with A8 = L, the chip will output a configuration code 7Fh. A further Device ID must be read with A8 = H.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2004/04/01
EN29F040A USER MODE DEFINITIONS
Standby Mode
The EN29F040A has a CMOS-compatible standby mode, which reduces the current to < 1A (typical). It is placed in CMOS-compatible standby when the CE pin is at VCC 0.5. The device also has a TTL-compatible standby mode, which reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the CE pin is at VIH. When in standby modes, the outputs are in a high-impedance state independent of the OE input.
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See "Reset Command" section. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.
Output Disable Mode
When the OE pin is at a logic high level (VIH), the output from the EN29F040A is disabled. The output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29F040A
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Write Mode
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 5 (Command Definitions) shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
COMMAND DEFINITIONS
The operations of the EN29F040A are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to the read mode.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29F040A
Table 5. EN29F040A Command Definitions
1
Addr
st nd rd th th th
Command Sequence Read/Reset Read Reset Read/Reset AutoSelect Manufacturer ID AutoSelect Device ID AutoSelect Sector Protect Verify Byte Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Notes:
Write Cycles Req'd
Write Cycle Data
2
Addr
3
Addr
4
Addr
5
Addr
6
Addr
Write Cycle Data
Write Cycle Data
Write Cycle Data
Write Cycle Data
Write Cycle Data
1 1 4 4 4 4 4 6 6 1 1
RA RD XXXh F0h 555h AAh 555h 555h 555h 555h 555h 555h xxxh xxxh AAh AAh AAh AAh AAh AAh B0h 30h
2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh
55h 55h 55h 55h 55h 55h 55h
555h 555h 555h 555h 555h 555h 555h
F0h 90h 90h 90h A0h 80h 80h
RA 000h/ 100h 001h/ 101h BA & 02h PA 555h 555h
RD 7Fh/ 1Ch 7Fh/ 04h 00h/ 01h PD AAh 2AAh 55h AAh 2AAh 55h
555h SA
10h 30h
RA = Read Address: address of the memory location to be read. This one is a read cycle. RD = Read Data: data read from location RA during Read operation. This one is a read cycle. PA = Program Address: address of the memory location to be programmed PD = Program Data: data to be programmed at location PA SA = Sector Address: address of the Sector to be erased. Address bits A18-A16 uniquely select any Sector.
The data is 00h for an unprotected sector and 01h for a protected sector.
Byte Programming Command
Programming the EN29F040A is performed on a byte-by-byte basis using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE or W E , whichever is last; data is latched on the rising edge of CE or W E , whichever is first. The program operation is completed when EN29F040A returns the equivalent data to the programmed location. Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is exceeded, DQ5 will produce a logical "1" and a Reset command can return the device to Read mode.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29F040A
Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and Chip/Sector Erase Operation Timings for timing waveforms.
Sector Erase Command
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations.
This device does not support multiple sector erase commands. Sector Erase operation will commence immediately after the first 30h command is written. The first sector erase operation must finish before another sector erase command can be given.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to "Write Operation Status" for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are "don't-cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29F040A
The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Contact Eon Silicon Solution, Inc. for
an additional supplement on this feature.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2004/04/01
EN29F040A WRITE OPERATION STATUS
DQ7 DATA Polling
The EN29F040A provides DATA Polling on DQ7 to indicate to the host system the status of the embedded operations. The DATA Polling feature is active during the Byte Programming, Sector Erase, Chip Erase, and Erase Suspend. (See Table 6) When the Byte Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the Byte Programming, an attempt to read the device will produce the true data last written to DQ7. For the Byte Programming, DATA polling is valid after the rising edge of the fourth WE or CE pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7 output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last rising edge of the sector erase W E or C E pulse.
DATA Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the address used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable ( OE ) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts. The flowchart for DATA Polling (DQ7) is shown on Flowchart 5. The DATA Polling (DQ7) timing diagram is shown in Figure 8.
DQ6 Toggle Bit I
The EN29F040A provides a "Toggle Bit" on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by toggling OE or CE ) will result in DQ6 toggling between "zero" and "one". Once the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the last rising edge of the Sector Erase W E pulse. The Toggle Bit is also active during the sector erase time-out window.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 s. The chip will then return to the read mode without changing data in all protected sectors. Toggling either CE or OE will cause DQ6 to toggle. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9.
DQ5 Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." (The Toggle Bit (DQ6) should also be checked at this time to make sure that the DQ5 is not a "1" due to the device having returned to read mode.) This is a failure condition that indicates the program or erase cycle was not successfully completed. . DATA
Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still function under this condition. Setting the CE to VIH will partially power down the device under those conditions.
The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.
DQ2 Erase Toggle Bit II
The "Toggle Bit" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Flowchart 6 shows the toggle bit algorithm, and the section "DQ2: Toggle Bit" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29F040A
completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Flowchart 6).
Table 6. Status Register Bits
DQ Name Logic Level `1' Definition Erase Complete or erase Sector in Erase suspend Erase On-Going Program Complete or data of non-erase Sector during Erase Suspend Program On-Going Erase or Program On-going Read during Erase Suspend Erase Complete Program or Erase Error Program or Erase On-going Chip Erase, Sector Erase or Erase suspend on currently addressed Sector. (When DQ5=1, Erase Error due to currently addressed Sector. Program during Erase Suspend on-going at current address Erase Suspend read on non Erase Suspend Sector
7
DATA
POLLING
`0' DQ7 DQ7 `-1-0-1-0-1-0-1-' DQ6 `-1-1-1-1-1-1-1-`
6
TOGGLE BIT
5
ERROR BIT
`1' `0'
`-1-0-1-0-1-0-1-' 2 TOGGLE BIT DQ2
Notes: DQ7 DATA
Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5 Error Bit: set to "1" if failure in programming or erase
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29F040A DATA PROTECTION
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE = VIL, W E = VIL and OE = VIH, the device will not accept commands on the rising edge of WE.
Low VCC Write Inhibit
During VCC power-up or power-down, the EN29F040A locks out write cycles to protect against any unintentional writes. If VCC < VLOK, the command register is disabled and all internal program or erase circuits are disabled. Under this condition, the device will reset to the READ mode. Subsequent writes will be ignored until VCC > VLKO.
Write "Noise" Pulse Protection
Noise pulses less than 5ns on OE , CE or WE will neither initiate a write cycle nor change the command register.
Logical Inhibit
If CE =VIH or WE=VIH, writing is inhibited. To initiate a write cycle, CE and W E must be a logical "zero". If CE , W E , and OE are all logical zero (not recommended usage), it will be considered a write.
Sector Protect and Unprotect
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operation in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Contact Eon Silicon Solution, Inc. for an additional supplement on this feature.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29F040A EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program Command Sequence (shown below)
Data Poll Device
Increment Address
No
Last Address?
Yes Programming Done
Flowchart 2. Embedded Program Command Sequence
See the Command Definitions section for more information.
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Flowchart 3. Embedded Erase
START
Write Erase Command Sequence (shown below)
Data Polling Device or Toggle Bit Successfully Completed
ERASE Done
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Flowchart 4. Embedded Erase Command Sequence
See the Command Definitions section for more information.
Chip Erase
Sector Erase
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Flowchart 5. DATA Polling Algorithm
Start
Read Data
DQ7 = Data? No No DQ5 = 1? Yes Read Data
Yes
DQ7 = Data? No Fail
Yes
Pass
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Flowchart 6. Toggle Bit Algorithm
Start
Read Data
No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Data
DQ6 = Toggle? Yes Fail
No
Pass
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +125C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . . . . -0.5 V to 7.0 V A9, OE# (Note 2) . . . . . . . . . . . . . . . -0.5 V to 11.5 V All other pins (Note 1) . . . . . . . . . . . . -0.5 V to Vcc+0.5V Output Short Circuit Current (Note 3) . . . . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot VSS to -1.0V for periods of up to 50 ns and to -2.0 V for periods of up to 20 ns. See Left Figure below. Maximum DC voltage on input and I/O pins is V CC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Right Figure below. Minimum DC input voltage on A9 pin is -0.5 V. During voltage transitions, A9 and OE# may undershoot VSS to -1.0V for periods of up to 50 ns and to -2.0 V for periods of up to 20 ns. See Left Figure. Maximum DC input voltage on A9 and OE# is 11.5 V which may overshoot to 12.5 V for periods up to 20 ns. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
2.
3.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (T A ) . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (T A ). . . . . . . . . . -40C to +85C VCC Supply Voltages VCC for 5% devices . . . . . . . . . . . . +4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . . . +4.50 V to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed.
Maximum Negative Overshoot Waveform
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Maximum Positive Overshoot Waveform 20
(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Table 7. DC Characteristics (Ta = 0C to 70C or - 40C to 85C; VCC = 5.0V 10%)
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current (read) TTL Byte Supply Current (Standby) TTL Supply Current (Standby) CMOS Supply Current (Program or Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS VID ILIT VLKO A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply voltage (Erase and Program lock-out) A9 = VID 3.2 IOL = 2 mA IOH = -2.5 mA IOH = -100 A 2.4 Vcc 0.4V 10.5 Test Conditions 0V VIN Vcc 0V VOUT Vcc Min Max 5 5 30 1.0 5.0 30 -0.5 2 0.8 Vcc + 0.5 0.45 Unit A A mA MA A mA V V V V V 11.5 100 4.2 V A V
CE = VIL; OE = VIH;
f = 6MHz
CE = VIH CE = Vcc 0.3V
Byte program, Sector or Chip Erase in progress
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Table 8. AC CHARACTERISTICS Read-only Operations Characteristics
Parameter Symbols JEDEC Standard Description Read Cycle Time Address to Output Delay Chip Enable To Output Delay Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time from Addresses, CE or OE , whichever occurs first Test Setup Min -45 45 45 45 25 10 10 0 Speed Options -55 55 55 55 30 15 15 0 -70 70 70 70 30 20 20 0 -90 90 90 90 35 20 20 0 Unit ns ns ns ns ns ns ns
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX
Notes: For -45, -55
tRC tACC tCE tOE tDF tDF tOH
CE = VIL OE = VIL OE = VIL
Max Max Max Max Max Min
Vcc = 5.0V 5% Output Load : 1 TTL gate and 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to 3.0 V Timing Measurement Reference Level, Input and Output: 1.5 V Vcc = 5.0V 10% Output Load: 1 TTL gate and 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V
For all others:
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Table 9. AC CHARACTERISTICS Write (Erase/Program) Operations
Parameter Symbols JEDEC Standard Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and DATA Polling Min Min Min Min Min Min MIn Min Min Min Min Min Min Typ Programming Operation Max Typ Sector Erase Operation Max Typ Chip Erase Operation Vcc Setup Time Rise Time to VID Max Min Min -45 45 0 35 20 0 0 0 10 0 0 0 25 20 7 200 0.3 5 3 35 50 500 Speed Options -55 55 0 45 25 0 0 0 10 0 0 0 30 20 7 200 0.3 5 3 35 50 500 -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 200 0.3 5 3 35 50 500 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 200 0.3 5 3 35 50 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s ns
tAVAV tAVWL tWLAX tDVWH tWHDX
tWC tAS tAH tDS tDH tOES tOEH
tGHWL tELWL tWHEH tWLWH tWHDL tWHWH1 tWHWH2 tWHWH3
tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tWHWH3 tVCS tVIDR
Read Recovery Time before Write ( OE High to W E Low)
CE SetupTime
CE Hold Time
Write Pulse Width Write Pulse Width High
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Table 10. AC CHARACTERISTICS Write (Erase/Program) Operations Alternate CE Controlled Writes
Parameter Symbols JEDEC Standard Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Read Enable Toggle and Hold Time Data Polling Read Recovery Time before Write ( OE High to CE Low)
W E SetupTime W E Hold Time
Speed Options -45 Min Min Min Min Min Min 0 10 Min Min Min Min Min Typ Programming Operation Max Typ Sector Erase Operation Max Typ Chip Erase Operation Vcc Setup Time Rise Time to VID Max Min Min 45 0 35 20 0 0 0 10 0 0 0 25 20 7 200 0.3 5 3 35 50 500 -55 55 0 45 25 0 0 0 10 0 0 0 30 20 7 200 0.3 5 3 35 50 500 -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 200 0.3 5 3 35 50 500 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 200 0.3 5 3 35 50 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s ns
tAVAV tAVEL tELAX tDVEH tEHDX
tWC tAS tAH tDS tDH tOES tOEH
tGHEL tWLEL tEHWH tELEH tEHEL tWHWH
1
tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 tWHWH3 tVCS tVIDR
Write Pulse Width Write Pulse Width High
tWHWH
2
tWHWH
3
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Table 11. ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Endurance Typ 0.3 3 7 2 100K Limits Max 5 35 200 5 Unit sec sec s Excludes system level overhead sec cycles Minimum 100K cycles guaranteed Comments Excludes 00H programming prior to erasure
Table 12. LATCH UP CHARACTERISTICS
Parameter Description Input voltage with respect to Vss on all pins except I/O pins (including A9 and OE ) Input voltage with respect to Vss on all I/O Pins Vcc Current Min -1.0 V -1.0 V -100 mA Max 12.0 V Vcc + 1.0 V 100 mA
Note : These are latch up characteristics and the device should never be put under these conditions. Refer to Absolute Maximum ratings for the actual operating limits.
Table 13. 32-PIN PLCC PIN CAPACITANCE @ 25C, 1.0MHz
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 4 8 8 Max 6 12 12 Unit pF pF pF
Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25C, 1.0MHz
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Table 15. DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
SWITCHING WAVEFORMS
Figure 5. AC Waveforms for READ Operations
Figure 6. AC Waveforms for Chip/Sector Erase Operations
Notes:
1. SA is the Sector address for Sector erase.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
SWITCHING WAVEFORMS (continued)
Figure 7. Program Operation Timings
Notes: 1. 2. 3. 4. 5. PA is address of the memory location to be programmed. PD is data to be programmed at byte address. /DQ7 is the output of the complement of the data written to the device. DOUT is the output of data written to the device. Figure indicates last two bus cycles of four bus cycle sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm Operations
Notes:
*DQ7 = Valid Data (The device has completed the embedded operation).
Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
Notes: *DQ6 stops toggling (The device has completed the embedded operation).
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
SWITCHING WAVEFORMS (continued)
Figure 10. Alternate /CE Controlled Write Operation Timings
Notes: 1. 2. 3. 4. 5. PA is address of the memory location to be programmed. PD is data to be programmed at byte address. /DQ7 is the output of the complement of the data written to the device. DOUT is the output of data written to the device. Figure indicates last two bus cycles of four bus cycle sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
ORDERING INFORMATION
EN29F040A
- 45
P
C
P PACKAGING CONTENT Blank= Conventional P=Pb free TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE P = 32 Plastic DIP J = 32 Plastic PLCC T = 32 Plastic TSOP
SPEED 45 = 45ns 55 = 55ns 70 = 70ns 90 = 90ns
BASE PART NUMBER EN = EON Silicon Solution Inc. 29F = FLASH, 5V 040 = 512K x 8 A = version A
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
PHYSICAL DIMENSIONS PL 032 X 32-Pin Plastic Leaded Chip Carrier
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
PHYSICAL DIMENSIONS (continued) PD 032 X 32-Pin Plastic DIP
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
33
(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A
PHYSICAL DIMENSIONS (continued) TS 032 X 32-Pin Standard Thin Small
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
34
(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01
EN29F040A Revisions List
Revision No Description Date
A B
Initial draft Correct a typo of table 5 on page 8.
Address bits A18-A16 uniquely select any Sector
2003/04/03 2004/04/01
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
35
(c)2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/04/01

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